New Device Model Simulation Evaluation: Methodologies, Standards, and Applications for Advanced Semi

New device model simulation evaluation verifies the accuracy, convergence, and robustness of compact models for advanced semiconductor devices such as SiC MOSFETs, GaN HEMTs, IGBTs, and nanoscale CMOS transistors. By benchmarking simulated DC, AC, transient, and thermal behavior against laboratory measurements in line with IEC, JEDEC, and GB standards, design teams can confidently deploy validated models in power electronics and integrated circuit workflows. This article explains the scope, samples, testing items, methods, and applications of professional device model simulation evaluation services.

Technical Overview

New device model simulation evaluation is the systematic process of extracting, verifying, and qualifying compact device models for use in circuit simulators and electronic design automation (EDA) environments. As wide-bandgap semiconductors, advanced process nodes, and novel transistor architectures enter mainstream production, the fidelity of their simulation models directly determines the reliability of design decisions made long before physical prototypes exist. A model that inaccurately predicts on-resistance, switching loss, or thermal behavior can lead to over-designed, costly products or, worse, field failures.

The evaluation covers several dimensions of model quality: parametric accuracy against measured device characteristics, numerical convergence across the intended operating envelope, temperature and bias dependence, scalability across device geometry, and computational efficiency within transient simulations. Models may be implemented as SPICE netlists, Verilog-A compact models, behavioral macromodels, or electro-thermal co-simulation modules, and each format requires a tailored validation strategy.

A professional evaluation workflow typically proceeds in four stages: sample device characterization on precision measurement equipment, model parameter extraction and fitting, model-versus-measurement benchmarking with quantified error metrics, and final robustness testing inside standard circuit simulator environments. The entire process is aligned with recognized standards frameworks, including the IEC 60747 series for discrete semiconductor devices, IEC 60749 for test methods, JEDEC guidelines for model documentation and quality, and applicable GB/T national standards.

Testing Samples

Silicon Power and Logic Device Models

Silicon-based compact models remain the backbone of analog and power design. Evaluation samples include SPICE models for low-voltage and high-voltage MOSFETs, insulated-gate bipolar transistors (IGBTs), fast-recovery and Schottky diodes, bipolar junction transistors, and CMOS transistor model libraries generated from advanced process design kits (PDKs). These models are assessed for threshold voltage accuracy, subthreshold behavior, output conductance, and body diode representation.

Wide-Bandgap Device Models

Silicon carbide (SiC) MOSFETs, SiC Schottky barrier diodes, gallium nitride (GaN) HEMTs, and GaN-on-Si power devices demand particularly rigorous model evaluation because of their fast switching edges, strong nonlinear capacitances, and unique trapping-related dynamic behavior. Samples include physics-based compact models, datasheet-derived behavioral models, and electro-thermal models intended for converter-level simulation.

Emerging and Novel Device Architectures

Model libraries for FinFETs, gate-all-around (GAA) nanosheet transistors, trench MOSFETs, superjunction devices, and experimental technologies such as gallium oxide and diamond devices are increasingly submitted for evaluation. These samples often require customized test structures, wafer-level probing, and advanced parameter extraction strategies that account for three-dimensional geometry effects.

Model Deliverables and Formats

Submitted samples may take the form of encrypted or plain-text SPICE model cards, Verilog-A source code, Saber MAST models, IBIS models for signal-integrity simulation, lookup-table-based behavioral models, or complete model packages containing documentation, example netlists, and application notes. Each deliverable is evaluated for completeness, portability across simulators, and compliance with the model documentation practices recommended by JEDEC and IEC.

Testing Items

The evaluation matrix for new device model simulation typically includes the following categories of testing items:

• DC characteristics: output curves, transfer curves, threshold voltage, on-resistance, transconductance, and leakage currents across bias and temperature.
• Capacitance and AC characteristics: gate-source, gate-drain, and drain-source capacitances, Ciss, Coss, and Crss behavior, reverse-transfer capacitance nonlinearity, and small-signal frequency response.
• Switching and transient characteristics: turn-on and turn-off times, rise and fall behavior, gate charge waveforms, switching energy losses, and reverse-recovery performance.
• Avalanche and breakdown behavior: breakdown voltage modeling, ruggedness under unclamped inductive switching, and safe operating area (SOA) boundary representation.
• Thermal and self-heating behavior: junction temperature dependence, transient thermal impedance networks, static and dynamic electro-thermal coupling, and thermal runaway prediction.
• Dynamic parameter effects: current collapse and dynamic on-resistance in GaN devices, threshold voltage hysteresis, and trapping-related dispersion.
• Numerical quality: convergence in DC, AC, and transient analyses, absence of non-physical discontinuities, charge conservation, and simulation runtime efficiency.
• Variability and statistical coverage: process corner models, Monte Carlo distribution consistency, and matching of model spread to measured device distributions.

Testing Methods

Reference Device Characterization

Golden-sample devices are characterized on calibrated laboratory equipment, including high-precision source-measure units for static I-V curves, impedance analyzers and CV meters for capacitance extraction, curve tracers for high-current and high-voltage punch-out, vector network analyzers for high-frequency S-parameters, and double-pulse test benches for switching characterization. Thermal characterization employs transient thermal impedance testers and infrared or temperature-sensitive parameter methods. All measurement setups follow procedures consistent with IEC 60747 and IEC 60749 test method guidance.

Model Extraction and Fitting

Measured data are processed through dedicated parameter extraction flows in which model equations are fitted to the characterization database. Optimization algorithms minimize the difference between simulated and measured curves, with weighted error functions that emphasize regions critical to the intended application, such as the subthreshold region for logic devices or the saturation knee for power converters.

Benchmarking and Error Quantification

The fitted model is simulated in standard circuit simulator environments under identical bias, temperature, and load conditions as the measurements. Results are compared using quantified metrics:

• Maximum absolute and relative error for each family of curves, with typical acceptance thresholds of a few percent for key parameters such as on-resistance and threshold voltage.
• Root-mean-square (RMS) error across the full bias sweep to capture global fitting quality.
• Switching energy deviation between simulated and double-pulse measured losses, commonly required to fall within a defined tolerance band for power device qualification.
• Thermal impedance curve deviation evaluated across the relevant pulse-width time constants.

Robustness and Convergence Testing

Validated models are stressed through canonical simulation scenarios, including hard-switched and soft-switched converter topologies, startup transients, extreme temperature sweeps, and mixed-signal co-simulation. Convergence statistics, timestep reductions, and simulation failures are recorded, and model boundaries beyond which extrapolation is unreliable are documented.

Documentation and Reporting

The final deliverable comprises a comprehensive evaluation report containing measured-versus-simulated overlays, tabulated error statistics, model validity ranges, identified limitations, and recommendations for simulator settings. Reports reference the applicable IEC, JEDEC, GB, and JIS documentation conventions so results remain traceable and auditable for customer quality systems aligned with ISO 9001 management frameworks.

Applications

Validated device models serve as foundational assets across the electronics industry:

• Electric vehicle powertrains: traction inverter design, battery management switching stages, and on-board charger development relying on accurate SiC and IGBT loss models.
• Renewable energy systems: photovoltaic string inverters, wind converters, and energy storage power conversion units that demand precise efficiency and thermal predictions.
• Data centers and telecom power: GaN-based high-density power supplies, LLC resonant converters, and 48 V architectures optimized through loss-accurate simulation.
• Consumer and industrial electronics: DC-DC regulators, motor drives, and white goods where switching-frequency and efficiency targets are set by model-driven design.
• Integrated circuit design: standard cell libraries, analog front ends, and mixed-signal blocks built on validated PDK transistor models across process corners.
• Reliability engineering: electro-thermal stress analysis, power cycling lifetime estimation, and derating studies based on validated self-heating models.
• Digital twin development: real-time hardware-in-the-loop simulation platforms requiring computationally efficient yet accurate device representations.

By performing model evaluation before design commit, organizations reduce prototype iterations, shorten development cycles, and avoid the cost of discovering model deficiencies during hardware validation.

FAQ

What accuracy level is typically required for a device model to pass evaluation?

Acceptance criteria depend on the application. For key static parameters such as on-resistance and threshold voltage, maximum errors of two to five percent are commonly specified. For switching energy in power devices, deviations within approximately ten percent of double-pulse measurements are often considered acceptable. The specific thresholds are agreed between the customer and the accredited third-party laboratory or evaluation provider before testing begins.

How does model evaluation differ from device qualification testing?

Device qualification verifies that physical components withstand environmental, electrical, and lifetime stress according to standards such as IEC 60749 or AEC-Q101-style automotive frameworks. Model evaluation instead assesses the mathematical representation of the device: how faithfully the model reproduces measured behavior and how reliably it converges in simulation. The two activities are complementary, and qualification-grade characterization data frequently feeds the model evaluation database.

Which simulation platforms are supported during evaluation?

Evaluation is performed on mainstream SPICE-family simulators as well as mixed-technology and electro-thermal simulation environments. Verilog-A based compact models are checked for language compliance and portability, and IBIS models are validated against the IBIS accuracy checklist methodology to ensure signal-integrity readiness.

How long does a complete model evaluation project take?

Timeline depends on device complexity and the number of test conditions. A single silicon MOSFET model with DC, capacitance, and switching benchmarks may be completed within one to two weeks, while a full electro-thermal GaN model library covering multiple geometries, temperatures, and dynamic effects can require several weeks of characterization, extraction, and statistical validation.

Can evaluation be performed on models without access to the underlying source code?

Yes. Encrypted or binary model files can be evaluated through black-box benchmarking, in which simulated outputs are compared against reference measurements without inspecting internal equations. This approach is common for vendor-supplied models and is fully supported under standard confidentiality arrangements with accredited third-party laboratories.