IC Substrate Lateral Coefficient of Thermal Expansion (CTE) Measurement: Methods, Standards, and App

The lateral (in-plane) coefficient of thermal expansion of an IC package substrate is a critical parameter that governs solder joint reliability, die stress, and warpage behavior in BGA, FCBGA, CSP, and SiP packages. This article provides a professional overview of lateral CTE (CTE-X and CTE-Y) testing for organic and ceramic IC substrates, covering sample preparation, TMA and dilatometry test methods, applicable standards such as ASTM E831 and IPC-TM-650, typical acceptance values, and frequently asked engineering questions.

Technical Overview

The lateral coefficient of thermal expansion (CTE), designated CTE-X and CTE-Y for the two in-plane axes of an IC package substrate, quantifies the dimensional change of the substrate parallel to its wiring plane per degree of temperature change, expressed in ppm/°C. Accurate lateral CTE determination is essential because a silicon die expands at only about 2.6 ppm/°C while a typical motherboard expands at 14–17 ppm/°C, and the package substrate must bridge this mismatch. Excessive lateral CTE differential drives solder joint fatigue, underfill delamination, low-k dielectric cracking, and excessive warpage during reflow, all of which degrade assembly yield and long-term reliability.

Unlike Z-axis (thickness) expansion, the lateral CTE of an IC substrate is strongly anisotropic and depends on construction variables. For this reason, both in-plane directions must be measured independently.

• Glass fabric weave: warp-direction fibers (usually panel X) constrain expansion more than fill-direction fibers (panel Y).
• Copper distribution: thick power and ground planes, with copper at roughly 17 ppm/°C, mechanically constrain the resin system and lower effective in-plane CTE.
• Resin system and filler loading: highly filled BT, ABF build-up films, and low-CTE core materials are engineered to hit target expansion values.
• Core versus coreless construction: coreless and embedded-trace substrates show different in-plane behavior than rigid glass-fabric cores.

Testing Samples

Organic Package Substrates

Lateral CTE testing applies to the full range of organic IC substrates, including BT resin/E-glass core substrates for BGA and memory packages, Ajinomoto build-up film (ABF) substrates for flip-chip BGA, coreless and embedded-trace designs for high-density fine-line packages, and metal-core or heat-spreader-integrated constructions.

Ceramic and Glass Substrates

Ceramic technologies including 96% and 99% alumina (Al2O3), LTCC, HTCC, and glass wafers or panels used for advanced fan-out and 2.5D interposer applications can be evaluated with the same in-plane methodology, typically with dilatometry for best precision at low expansion levels.

Coupon Geometry and Preparation

Standard TMA coupons are rectangular strips of 6–10 mm length and approximately 3 mm width, cut at full panel thickness along the substrate X and Y axes. Preparation requirements include:

• Long edges machined or precision-cut parallel, typically within ±25 µm, to ensure true axial displacement measurement.
• Optional copper etching to bare laminate when the specification targets the dielectric material rather than the finished substrate.
• Dry bake at 105 °C for 2 hours followed by desiccator cooling to remove absorbed moisture.
• Minimum three specimens per direction per lot to capture panel-level variability.

Testing Items

Typical reported test items for lateral CTE characterization include:

• In-plane CTE in the X direction (warp axis), reported in ppm/°C.
• In-plane CTE in the Y direction (fill axis), reported in ppm/°C.
• In-plane anisotropy ratio, calculated as CTE-X divided by CTE-Y.
• Alpha 1 expansion below the glass transition temperature (Tg).
• Alpha 2 expansion above Tg for applications that see temperatures beyond the transition region.
• Segmented range values such as 25–125 °C, 30–150 °C, or 25–260 °C for reflow-condition simulation.
• TMA-measured glass transition temperature and the change in expansion slope at the transition.
• Optional Z-axis CTE on companion coupons for complete three-axis expansion characterization.

Typical measurement uncertainty for a competent laboratory is within ±0.3 to 0.5 ppm/°C, or approximately ±5% of reading, whichever is greater.

Testing Methods

Thermomechanical Analysis (TMA) — Primary Method

TMA per ASTM E831 and ISO 11359-2, adapted from IPC-TM-650 Method 2.4.24 principles, is the industry-standard technique for lateral CTE of IC substrates. The rectangular coupon is placed horizontally beneath a flat-tipped fused silica probe with a small static force of roughly 0.02–0.2 N. The furnace ramps at typically 5 °C/min under a 20–50 mL/min nitrogen purge, and probe displacement is recorded continuously. CTE is computed from the slope of the dimensional change divided by initial length versus temperature, multiplied by 10 to the 6th power to obtain ppm/°C. A two-run protocol is standard: the first scan relieves residual cure and mechanical stress, and reported data are taken from the second scan.

Horizontal Push-Rod Dilatometry

For ceramic substrates and other low-expansion materials, push-rod dilatometry per ASTM E228 offers superior precision. Coupons of 25–50 mm length rest in a fused silica holder with displacement resolution below 0.05 µm, making the method well suited to verifying alumina, LTCC, and glass values in the 3–8 ppm/°C range and for calibrating against certified reference materials such as sapphire or fused silica.

Strain Gauge and Digital Image Correlation (DIC)

For full-panel characterization, high-temperature foil strain gauges bonded to substrate surfaces inside an environmental chamber provide local expansion data, while stereo digital image correlation delivers non-contact full-field strain maps during thermal ramping. These methods reveal local CTE variation near dense copper planes, cavity regions, and panel edges that coupon-level TMA cannot resolve.

Standard Test Conditions

• Temperature range: 30–260 °C standard; −40–260 °C for automotive-grade qualification.
• Heating rate: 5 °C/min nominal, with 3 °C/min acceptable for high-resolution Tg determination.
• Atmosphere: high-purity nitrogen purge to prevent oxidation of copper surfaces.
• Preconditioning: 105 °C / 2 h dry bake with desiccator cooling before testing.
• Sampling: minimum three coupons per direction, per panel location, per lot.

Applications

• Supplier qualification and incoming lot release for FCBGA, BGA, CSP, and SiP package substrates.
• Warpage simulation inputs for finite element models and JEDEC-style coplanarity prediction across reflow profiles.
• Solder joint thermal fatigue life assessment driven by CTE mismatch between substrate, die, and board.
• New material development, including low-CTE cores, highly filled build-up films, and matched-expansion ceramic interposers.
• Failure analysis comparison of field-failed or reliability-failed substrates against known-good reference lots.
• Automotive and high-reliability qualification programs requiring documented CTE control from −40 °C to peak reflow temperature.
• Process change management, such as evaluating the effect of lamination, cure, or copper plating adjustments on dimensional stability.

FAQ

Why must lateral CTE be measured separately from thickness-direction CTE?

IC substrates are mechanically anisotropic. The glass fabric and copper planes constrain in-plane expansion while resin expansion is largely free in the Z direction, so thickness CTE is typically two to four times higher than lateral CTE. Warpage, solder joint stress, and die stress depend on the in-plane values, which is why both axes must be measured independently.

What lateral CTE values are typically specified for IC substrates?

Common acceptance windows are 10–16 ppm/°C for glass-fabric BT core substrates, 7–12 ppm/°C for low-CTE core designs, 20–40 ppm/°C for unfilled build-up film layers in isolation, 6.5–7.5 ppm/°C for alumina ceramic, and 3–8 ppm/°C for silicon-matched interposer constructions, always measured below Tg unless otherwise specified.

How are the X and Y directions defined on a substrate panel?

By convention, X is aligned with the warp direction of the glass fabric, which is the primary reinforcement direction, and Y is aligned with the fill direction. Because panel manufacturing introduces directional bias, coupons must be cut and labeled according to the panel coordinate system, and results reported separately for each axis.

Does the copper on the substrate affect the measured lateral CTE?

Yes. Copper at approximately 17 ppm/°C mechanically constrains the polymer composite, so a finished substrate with heavy copper planes measures lower in-plane CTE than the bare laminate. Specifications must state whether coupons are tested as fabricated or after copper etching to bare dielectric, since the two conditions are not interchangeable.

When should TMA be used instead of dilatometry?

TMA is preferred for thin organic substrates, small coupons sizes, and simultaneous Tg determination. Dilatometry is preferred for ceramics, glass, and low-expansion materials where longer specimens and sub-micron displacement resolution deliver better accuracy, and when calibration traceability to ASTM E228 reference materials is required.

Why is a second heating run recommended for reporting?

The first thermal scan relieves residual stresses from lamination, cure, and pattern processing and may show post-cure shrinkage. Data from the second run represent the stabilized expansion behavior the substrate exhibits during actual assembly and service thermal cycles, providing reproducible and comparable CTE values.